{
 "cells": [
  {
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   "metadata": {},
   "source": [
    "Veriloggen by examples\n",
    "====================\n"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Empty Module\n",
    "--------------------"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 2,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "\n",
      "\n",
      "module empty\n",
      "(\n",
      "  input CLK,\n",
      "  input RST\n",
      ");\n",
      "\n",
      "\n",
      "endmodule\n",
      "\n",
      "\n"
     ]
    }
   ],
   "source": [
    "from __future__ import absolute_import\n",
    "from __future__ import print_function\n",
    "from veriloggen import *\n",
    "\n",
    "m = Module('empty')\n",
    "clk = m.Input('CLK')\n",
    "rst = m.Input('RST')\n",
    "\n",
    "rtl = m.to_verilog()\n",
    "print(rtl)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Combinational Circuit\n",
    "--------------------"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "### Input/Output/Reg/Wire"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 14,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "\n",
      "\n",
      "module comb\n",
      "(\n",
      "  input CLK,\n",
      "  input RST,\n",
      "  input a,\n",
      "  output b\n",
      ");\n",
      "\n",
      "  reg c;\n",
      "  wire d;\n",
      "\n",
      "endmodule\n",
      "\n",
      "\n"
     ]
    }
   ],
   "source": [
    "m = Module('comb')\n",
    "clk = m.Input('CLK')\n",
    "rst = m.Input('RST')\n",
    "\n",
    "a = m.Input('a')\n",
    "b = m.Output('b')\n",
    "c = m.Reg('c')\n",
    "d = m.Wire('d')\n",
    "\n",
    "rtl = m.to_verilog()\n",
    "print(rtl)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "### Multi-bit signal"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 15,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "\n",
      "\n",
      "module comb\n",
      "(\n",
      "  input CLK,\n",
      "  input RST,\n",
      "  input [8-1:0] a,\n",
      "  output [8-1:0] b\n",
      ");\n",
      "\n",
      "  reg [16-1:0] c;\n",
      "  wire [20-1:0] d;\n",
      "\n",
      "endmodule\n",
      "\n",
      "\n"
     ]
    }
   ],
   "source": [
    "m = Module('comb')\n",
    "clk = m.Input('CLK')\n",
    "rst = m.Input('RST')\n",
    "\n",
    "a = m.Input('a', 8)\n",
    "b = m.Output('b', width=a.width)\n",
    "c = m.Reg('c', 16)\n",
    "d = m.Wire('d', c.width + 4)\n",
    "\n",
    "rtl = m.to_verilog()\n",
    "print(rtl)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "### Parameter and Localparam"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 16,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "\n",
      "\n",
      "module comb #\n",
      "(\n",
      "  parameter sig_width = 8\n",
      ")\n",
      "(\n",
      "  input CLK,\n",
      "  input RST,\n",
      "  input [sig_width-1:0] a,\n",
      "  output [sig_width-1:0] b\n",
      ");\n",
      "\n",
      "  reg [sig_width-1:0] c;\n",
      "  wire [sig_width+4-1:0] d;\n",
      "\n",
      "endmodule\n",
      "\n",
      "\n"
     ]
    }
   ],
   "source": [
    "m = Module('comb')\n",
    "clk = m.Input('CLK')\n",
    "rst = m.Input('RST')\n",
    "\n",
    "sig_width = m.Parameter('sig_width', 8)\n",
    "\n",
    "a = m.Input('a', sig_width)\n",
    "b = m.Output('b', a.width)\n",
    "c = m.Reg('c', a.width)\n",
    "d = m.Wire('d', c.width + 4)\n",
    "\n",
    "rtl = m.to_verilog()\n",
    "print(rtl)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "### Substitution and Assign"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 21,
   "metadata": {},
   "outputs": [
    {
     "data": {
      "text/plain": [
       "<veriloggen.core.vtypes.Subst at 0x10c721ad0>"
      ]
     },
     "execution_count": 21,
     "metadata": {},
     "output_type": "execute_result"
    }
   ],
   "source": [
    "m = Module('comb')\n",
    "clk = m.Input('CLK')\n",
    "rst = m.Input('RST')\n",
    "\n",
    "a = m.Input('a', 8)\n",
    "b = m.Output('b', 8)\n",
    "c = m.Wire('c', 8)\n",
    "d = m.Wire('d', 8)\n",
    "\n",
    "# Substitusion\n",
    "c(a + 1)  # --> Subst object representing \"c <- a + 1\""
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 25,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "\n",
      "\n",
      "module comb\n",
      "(\n",
      "  input CLK,\n",
      "  input RST,\n",
      "  input [8-1:0] a,\n",
      "  output [8-1:0] b\n",
      ");\n",
      "\n",
      "  wire [8-1:0] c;\n",
      "  wire [8-1:0] d;\n",
      "  assign c = a + 1;\n",
      "  assign d = a + 2;\n",
      "\n",
      "endmodule\n",
      "\n",
      "\n"
     ]
    }
   ],
   "source": [
    "m = Module('comb')\n",
    "clk = m.Input('CLK')\n",
    "rst = m.Input('RST')\n",
    "\n",
    "a = m.Input('a', 8)\n",
    "b = m.Output('b', 8)\n",
    "c = m.Wire('c', 8)\n",
    "d = m.Wire('d', 8)\n",
    "\n",
    "# Assign requires Substitution object\n",
    "m.Assign(c(a + 1))\n",
    "\n",
    "# var.assign() method returns same result\n",
    "d.assign(a + 2)\n",
    "\n",
    "rtl = m.to_verilog()\n",
    "print(rtl)"
   ]
  }
 ],
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